OpenCollector Database

asco 0.4.7	Category: tool
ascodev 1 August 2010; 10:08

ASCO is a SPICE circuit optimizer used to design high performance analog low-power low-voltage circuits for mobile communications. The key features of the ASCO tool are:

Simulator independent: currently out-of-the-box support for Eldo (TM), HSPICE (R), LTSpice (TM), Spectre (R) and Qucs exist. More are to be included in future releases.
Number of variables: there is, in theory, no limit to the number of circuit variables that can be optimized, except those constraints imposed by the available computer memory and/or the time required to generate a functional circuit. It is currently hardcoded in the C code.
PVT corners: by using the simulator functionality, the possibility to test various design corners and Monte Carlo analysis is only limited to the simulator capability and by the time it takes to finish the optimization.
Efficiency: the optimization algorithm features a global optimization using differential evolution. It has been used on a variety of applications and is know to produce good results in an acceptable time.
Within the supported SPICE simulators, arbitrary netlist can be optimized on different conditions without having to recompile the code.
File format: all outputted data and log information is stored in plain text format. This guarantees that they will be always readable in the future. In addition, it makes possible to use other existing tools to post-process the optimization results.

Update

Corrected multiprocessor optimization algorithm message truncation error related to MPI_SCATTERV function.

Corrected load balancer implementation.

RF module better supports Spectre.

Support for LTspice and Spectre in the 'postp' tool.

Code clean-up and minor improvements.

License: GPL

ngspice rework-21	Category: tool
Paolo Nenzi 22 June 2010; 12:19

Ngspice is a mixed-level/mixed-signal circuit simulator based on three open source software packages: Spice3f5, Cider1b1, and Xspice. Spice3 is the most famous and widely used circuit simulator. Cider is mixed-level simulator that includes Spice3f5 and adds DSIM, a device simulator. Cider couples the circuit level simulator to the device simulator to provide greater simulation accuracy (at the expense of greater simulation time). Xspice is an extension to Spice3 that provides code modeling support and simulation of digital components through an embedded event driven algorithm.

Update

Several bugs have been fixed improving ngspice stability and reliability. New features and devices have been introduced:

Added compatibility mode for dealing with other simulators.
BSIM 4 and BSIMSOI devices updated
Transmission lines, B source and PML source handling improved
New interface options, including pipe mode, improved measures, and tabulated data output

Updated documentation is now available as a separate package in pdf.

License: BSD

VHD2VL 2.3	Category: tool
Larry Doolittle 3 May 2010; 12:40

vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthesisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.

Update
Now understands hex and octal strings, rems in many more places, more real-life port mappings (including "open"), single un-named generic map items, array type, inout ports, generics and generate, and much much more!

License: GPL

Mr.Filter 0.2.1	Category: tool
Alan Somers 28 April 2010; 16:22

An active filter design assistant. Electrical engineers can use it to design and simulate analog active filters.

License: GPL

Covered 0.7.8	Category: tool
Trevor Williams 25 March 2010; 00:43

Covered is a Verilog code coverage utility that reads in a Verilog design and generated VCD/LXT dumpfile (or runnable in VPI module form) from that design and generates a coverage file that can be merged with other coverage files and/or used to create a coverage report. Covered also contains the coverage report utility that reads in a coverage file to produce human-readable coverage reports viewable in ASCII or GUI form. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state and FSM state transition, and assertion coverage.

Update
Bug fix release and enhancements for Verilog language support.

License: GPL

SVEditor 0.1.1	Category: tool
Matthew Ballance 8 February 2010; 00:06

SVEditor is an Eclipse-based editor for SystemVerilog and Verilog files.

Update
SVEditor 0.1.1 adds source indenting and auto-indenting support.

License: Other

layout editor 20091228	Category: tool
J. Thies 27 December 2009; 06:48

A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, crossplatform compatible, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form), Gerber, LEF, DEF, ...

Update
New features: direct load of gzip'ed files, support of compressed blocks in saving OASIS, automatic mapping of layer/datatype possible, SOURCE file format, increase layers to 1024, new setup of used layers (default 128), new mosis example library, photonic devices in the shape library, new distributions (e.g fedora 12), ...

License: GPL

YASEP 2009	Category: design
Yann Guidon 18 October 2009; 02:06

YASEP (Yet Another Small Embedded Processor) is a configurable microprocessor core (16 or 32 bits, instruction set and other features...) written in VHDL and designed with HTML+JavaScript. The website is completely downloadable and contains tightly integrated resources: documentation, assembler, disassembler, configurator, self-tests. The website is more than an IDE because the same tools are used for designing/defining the core AND using it ! And the learning curve is very smooth since there is NO tool or software to get, install and learn.

License: Other

The TimingAnalyzer 0.931	Category: tool
30 August 2009; 10:34

A tool for drawing timing diagrams and performing timing analysis. It is written in java and runs on JRE/JDK 1.6.0. Tool supports python scripting.

License: Other

Toped O.94	Category: tool
gs 7 August 2009; 18:58

Toped is an open source cross-platform IC layout editor, based on openGL and wxWidgets. The project defines its own scripting language - TELL, capable not only of configuring the editor properties, but also of coding and facilitating layout generation. All operations are executed as a response to a TELL command. There is no need to type every command - each menu item or shortcut generates one. The main focus is on the speed of the rendering and the details and quality of the layout view. The user is free to use the full power of openGL in terms of colors and fill patterns. Output can be exported to GDSII.

Update

New graphic renderer (Requires OpenGL 1.4 support). Rendering speed improved by up to 3 times. Old rendering remains for platforms with limited OpenGL support.
Updates of the internal layout database to improve the speed and memory footprint.
GDSII rendering updates and optimizations.

License: GPL

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