vhd2vl is a VHDL to Verilog translation program.
It targets the translation of synthesisable RTL.
While far from complete it supports a useful
subset of VHDL, sufficient for complex designs.
Now understands hex and octal strings, rems in many more places,
more real-life port mappings (including "open"), single un-named
generic map items, array type, inout ports, generics and generate,
and much much more!